This image represents a Ti/Ni/Cu under-bump metallization stack used in wafer bumping, highlighting the layered metal structure that supports reliable flip-chip interconnects and advanced semiconductor packaging.

Ti/Ni/Cu UBM Stack Design: Principles, Process Control, and Reliability Considerations

Under-bump metallization (UBM) is one of the most critical yet least visible elements of wafer-level packaging. While solder bumps, copper pillars, and micro-bumps often receive the most attention, the long-term electrical and mechanical reliability of any bumped interconnect depends heavily on the integrity of the UBM stack beneath it. Among the various UBM architectures used in modern semiconductor manufacturing, the Ti/Ni/Cu stack has become one of the most widely adopted due to its balance of adhesion, diffusion control, and solder compatibility.

Ti/Ni/Cu UBM stacks are commonly used in flip-chip, wafer-level packaging, fan-out packaging, and advanced interposer-based designs. Their success lies in the clear functional separation of layers, where each metal serves a specific role in supporting bump formation and long-term reliability. However, designing and manufacturing a robust Ti/Ni/Cu UBM stack requires careful attention to materials, thickness control, deposition methods, and downstream interactions.

This article provides a comprehensive explanation of Ti/Ni/Cu UBM stack design, focusing on why it is used, how each layer functions, how the stack is manufactured, and what failure mechanisms must be avoided.

The Role of UBM in Wafer Bumping

Under-bump metallization serves as the interface between the die pad and the external bump. Without UBM, solder or copper bumps would not adhere reliably to aluminum or copper pads, nor would they maintain stable electrical performance over time.

A properly designed UBM stack performs several essential functions simultaneously. It must adhere strongly to the underlying pad, block unwanted diffusion between materials, provide a surface that wets uniformly during bump formation, and remain mechanically stable throughout thermal cycling and electrical operation.

UBM design failures often do not manifest immediately. Instead, they appear later as solder joint fatigue, intermetallic overgrowth, delamination, or open circuits after reliability testing. As a result, UBM stack design is as much about long-term behavior as it is about initial manufacturability.

Why Ti/Ni/Cu Is a Popular UBM Stack

The Ti/Ni/Cu UBM stack has become a standard choice because it provides a clear division of labor between layers while remaining compatible with common wafer bumping processes.

Titanium offers strong adhesion to aluminum and copper pads. Nickel acts as a diffusion barrier and intermetallic control layer. Copper provides a highly conductive, solder-wettable surface and integrates well with electroplating processes.

Together, these layers form a robust foundation for solder bumps, copper pillars, and hybrid bump structures. The stack is flexible enough to support a wide range of bump materials while maintaining predictable reliability performance.

Titanium Layer: Adhesion and Interface Control

The titanium layer is the foundation of the Ti/Ni/Cu UBM stack. Its primary role is adhesion to the underlying pad, which is typically aluminum or copper.

Titanium forms strong chemical bonds with aluminum oxide and copper surfaces, allowing it to anchor the UBM stack securely to the wafer. Without this adhesion layer, the entire UBM stack is vulnerable to delamination during thermal cycling or mechanical stress.

Titanium is typically deposited using physical vapor deposition (PVD) to achieve a thin, uniform layer. Thickness control is critical. If the titanium layer is too thin, adhesion may be insufficient. If it is too thick, stress buildup and cracking can occur.

Because titanium oxidizes readily, it must be covered quickly by the next layer in the stack to prevent excessive oxide formation that could compromise electrical performance.

Nickel Layer: Diffusion Barrier and Reliability Anchor

The nickel layer is arguably the most important component of the Ti/Ni/Cu UBM stack from a reliability standpoint. Its primary function is to act as a diffusion barrier between the pad metal and the bump material.

In solder-bumped applications, nickel limits the growth of brittle intermetallic compounds that can form when solder reacts directly with copper or aluminum. By controlling intermetallic formation, nickel helps maintain mechanical integrity over long-term thermal cycling.

Nickel also contributes to mechanical robustness by providing a relatively hard, stable layer that resists deformation during bump formation and reflow.

Nickel thickness is a key design parameter. Too thin, and diffusion control becomes ineffective. Too thick, and internal stress may increase, leading to cracking or delamination. Electroplated nickel is commonly used because it allows precise thickness control and good uniformity across the wafer.

Copper Layer: Wettability and Electrical Performance

The copper layer serves as the top surface of the Ti/Ni/Cu UBM stack and plays a critical role during bump formation. Copper provides excellent wettability for solder and integrates seamlessly with copper pillar and electroplating processes.

From an electrical standpoint, copper offers low resistivity and high current-carrying capability, making it ideal for power and high-speed signal applications.

Copper thickness must be optimized carefully. It must be thick enough to ensure uniform bump formation and robust electrical conduction, but not so thick that it introduces excessive stress or interferes with lithographic patterning.

Copper is typically deposited by electroplating over a thin seed layer, allowing high throughput and precise geometry control.

Deposition Methods and Process Integration

The Ti/Ni/Cu UBM stack is typically formed using a combination of PVD and electroplating processes.

Titanium and an initial copper seed layer are usually deposited by PVD to ensure good adhesion and step coverage. Nickel and bulk copper layers are then electroplated to achieve the desired thickness.

Lithography is used to define the UBM footprint, ensuring that the stack aligns precisely with the pad openings and passivation windows.

Process integration is critical. Poor alignment, contamination between steps, or inconsistent plating conditions can lead to non-uniform UBM thickness, which directly affects bump coplanarity and assembly yield.

Thickness Optimization and Stack Balance

Thickness optimization is one of the most important aspects of Ti/Ni/Cu UBM design. Each layer must be thick enough to perform its function without introducing unnecessary stress or cost.

Typical design considerations include:

• Sufficient titanium thickness for adhesion without excessive stress

• Nickel thickness adequate to block diffusion over product lifetime

• Copper thickness optimized for wettability and current carrying

Thickness ratios are often tuned based on application requirements, such as fine-pitch micro-bumps versus large solder bumps for power devices.

Interaction with Solder and Copper Pillar Bumps

The Ti/Ni/Cu stack behaves differently depending on the bump technology used.

In solder bumping, nickel directly interacts with the solder alloy to form intermetallic compounds. Controlled intermetallic growth is essential for reliability, and nickel thickness plays a major role in determining intermetallic morphology.

In copper pillar bumping, the copper layer becomes part of the pillar structure. Nickel continues to act as a diffusion barrier, while copper provides mechanical height and electrical conduction.

UBM design must therefore be tailored to the specific bumping process rather than treated as a one-size-fits-all solution.

Common Failure Modes in Ti/Ni/Cu UBM Stacks

Despite its robustness, the Ti/Ni/Cu stack is not immune to failure. Common failure mechanisms include:

• Titanium delamination due to poor adhesion or contamination

• Nickel cracking caused by excessive stress or improper thickness

• Copper corrosion or oxidation if exposed

• Excessive intermetallic growth during high-temperature operation

Many of these failures are latent and only appear during reliability testing, making early detection challenging.

Reliability Testing and Qualification

Ti/Ni/Cu UBM stacks must be validated through extensive reliability testing. Common tests include thermal cycling, thermal shock, humidity exposure, and power cycling.

Successful UBM designs show stable interfacial integrity, controlled intermetallic growth, and minimal resistance change over time.

Cross-section analysis and failure mode tracking are essential tools for confirming that the UBM stack performs as intended.

Design Considerations for Advanced Packaging

As packaging technologies evolve toward finer pitches and heterogeneous integration, Ti/Ni/Cu UBM stacks must adapt.

Advanced designs may require thinner layers, tighter lithography control, and compatibility with redistribution layers and fan-out structures.

Close collaboration between design, wafer fabrication, and backend assembly teams is essential to ensure that UBM design supports both manufacturability and long-term reliability.

Backend Manufacturing Support with Silicon Craft Technologies

Designing and qualifying robust Ti/Ni/Cu UBM stacks requires deep understanding of materials, process integration, and reliability behavior. Silicon Craft Technologies provides backend manufacturing support to help customers optimize UBM stack designs for wafer bumping and advanced packaging.

With experience spanning UBM material selection, thickness optimization, process integration, and reliability validation, Silicon Craft Technologies works with customers to reduce risk, improve yield, and ensure long-term interconnect stability.

Conclusion

Ti/Ni/Cu UBM stack design is a foundational element of modern wafer bumping and flip-chip packaging. Each layer plays a critical role in adhesion, diffusion control, wettability, and electrical performance.

A well-designed UBM stack enables reliable interconnects, stable manufacturing, and long product lifetimes. Poorly designed stacks, by contrast, introduce latent risks that can undermine even the most advanced packaging technologies.

As semiconductor packaging continues to advance, careful Ti/Ni/Cu UBM design will remain essential to bridging the gap between wafer fabrication and reliable system-level performance.